发送机代码：
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYCERTIFICATIONIS
PORT(IN_A:INSTD_LOGIC_VECTOR(7DOWNTO0);
OUT_A:OUTSTD_LOGIC_VECTOR(8DOWNTO0)
);
ENDCERTIFICATION;
ARCHITECTUREONEOFCERTIFICATIONIS
BEGIN
PROCESS(IN_A)
VARIABLEA:STD_LOGIC_VECTOR(3DOWNTO0);
BEGIN
A:=0000;
FORNIN0TO7LOO
IFIN_A(N)=1THEN
A:=A+1;
ENDIF;
ENDLOOP;
OUT_A(8DOWNTO1)=IN_A(7DOWNTO0);
OUT_A(0)=NOT(A(0));
ENDPROCESS;
ENDONE;
接受机代码：
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYRECEIVEIS
PORT(IN_B:INSTD_LOGIC_VECTOR(8DOWNTO0);
OUT_B:OUTSTD_LOGIC_VECTOR(7DOWNTO0);
INSTRUCTION:OUTSTD_LOGIC
);
ENDRECEIVE;
ARCHITECTUREONEOFRECEIVEIS
BEGIN
PROCESS(IN_B)
VARIABLEA:STD_LOGIC_VECTOR(3DOWNTO0);
BEGIN
A:=0000;
FORNIN0TO8LOOP
IFIN_B(N)=1THEN
A:=A+1;
ENDIF;
ENDLOOP;
OUT_B(7DOWNTO0)=IN_B(8DOWNTO1);
IFA(0)=1THEN
INSTRUCTION=1;
ELSE
INSTRUCTION=0;
ENDIF;
ENDPROCESS;
ENDONE;
器件原理图：
器件波形图：